1. Field of the Invention
The present invention relates to a thin-film magnetic memory device, and particularly to a random access memory provided with memory cells having MTJs (magnetic tunnel junctions)
2. Description of the Background Art
Attention is being given to an MRAM (Magnetic Random Access Memory) device as a memory device, which can nonvolatilely store data with a low power consumption. The MRAM device is a memory device, in which a plurality of thin-film magnetic members are formed in a semiconductor integrated circuit for nonvolatilely storing data, and random access to each thin-film magnetic member is allowed.
Particularly, in recent years, it has been announced that a performance of the MRAM device can be dramatically improved by using the thin-film magnetic members, which utilize the MTJs, as memory cells. The MRAM device with memory cells having the magnetic tunnel junction has been disclosed in technical references such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000 and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 21 conceptually shows a structure of a memory cell, which has a magnetic tunnel junction, and will also be referred to merely as an “MTJ memory cell” hereinafter.
Referring to FIG. 21, an MTJ memory cell MC includes a magnetic tunnel junction MTJ having an electric resistance, which is variable in accordance with a data level of storage data magnetically written thereinto, and an access transistor ATR. Access transistor ATR is connected in series to magnetic tunnel junction MTJ, and is arranged between a read bit line RBL and a write bit line WBL. A field-effect transistor is typically used as access transistor ATR.
For the MTJ memory cell, there are arranged write bit line WBL and a write digit line WDL for passing a data write current in a data write operation as well as a word line WL for instructing data reading and read bit line RBL for reading out storage data in a data read operation.
FIG. 22 shows a structure of the MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 22, access transistor ATR is formed on a semiconductor main substrate SUB. Access transistor ATR has source/drain regions 110 and 120 formed of n-type regions as well as a gate 130. Source/drain region 110 is electrically coupled to read bit line RBL via a metal film 140 formed in a contact hole.
Write digit line WDL is formed on a metal wiring layer at a higher level than read bit line RBL. Magnetic tunnel junction MTJ is electrically coupled to source/drain region 120 of access transistor ATR via metal film 140 formed in the contact hole, metal wiring layers and barrier metal 150. Barrier metal 150 is a buffer member provided for electrically coupling magnetic tunnel junction MTJ and the metal wiring.
Magnetic tunnel junction MTJ has a magnetic material layer, which has a fixed-magnetization direction, and will also be referred merely to as a “fixed-magnetic layer” hereinafter, and a magnetic material layer VL, which is magnetized in a direction depending on a data-write magnetic field caused by a data-write current, and will also be referred merely to as a “free-magnetic layer” hereinafter. A tunneling barrier TB formed of an insulator film is disposed between fixed-magnetic layer FL and free-magnetic layer VL. Free-magnetic layer VL is magnetized in the same direction as fixed-magnetic layer FL or in the opposite direction in accordance with the level of the storage data to be written.
Magnetic tunnel junction MTJ has an electric resistance, which is variable depending on a correlation in magnetization direction between fixed-magnetic layer FL and free-magnetic layer VL. More specifically, when the fixed-magnetic layer FL and free-magnetic layer VL are magnetized in the same parallel direction, the electric resistance is smaller than that in the case where these magnetic layers FL and VL are magnetized in the opposite (anti-parallel) directions, respectively.
Write bit line WBL is electrically coupled to magnetic tunnel junction MTJ, and is arranged at a higher level than magnetic tunnel junction MTJ. As will be described later in greater detail, it is necessary to pass the data write current through both of write bit line WBL and write digit line WDL in a data write operation. In a data read operation, however, word line WL is activated to carry a high voltage so that access transistor ATR is turned on, and magnetic tunnel junction MTJ is electrically coupled between read bit line RBL and write bit line WBL.
Write bit line WBL and write digit line WDL for passing a data write current as well as read bit line RBL for passing a sense current (data read current) are formed in metal wiring layers. Word line WL is provided for controlling a gate voltage of access transistor ATR, and it is not necessary to pass actively a current therethrough. Accordingly, for improving a density or degree of integration, word line WL is not formed in an independent or dedicated metal interconnection layer, but is formed in the same interconnection layer as gate 130 by using a polycrystalline silicon layer or a polycide layer.
FIG. 23 conceptually shows an operation of writing data in the MTJ memory cell.
Referring to FIG. 23, word line WL is inactive, and access transistor ATR is turned off in the data write operation. In this state, the data write currents for magnetizing free-magnetic layer VL in the direction depending on the level of the write data are supplied to write bit line WBL and write digit line WDL, respectively. The magnetization direction of free-magnetic layer VL depends on the directions of respective data write currents flowing through write bit line WBL and write digit line WDL.
FIG. 24 conceptually shows a relationship between the direction of the data write current and the magnetization direction of the free-magnetic layer.
Referring to FIG. 24, a magnetic field Hx given by an abscissa represents a direction of a magnetic field H(WDL) produced by the data write current flowing through write digit line WDL. A magnetic field Hy given by an ordinate represents a direction of magnetic field H(WBL) caused by the data write current flowing through write bit line WBL. The magnetization direction of free-magnetic layer VL is updated only when a sum of magnetic fields H(WDL) and H(WBL) is in a region outside an asteroid characteristic line depicted in FIG. 24. More specifically, it is necessary for executing the data writing to pass the data write currents, which are large enough to cause a magnetic field exceeding a predetermined intensity, through both write digit line WDL and write bit line WBL.
When a magnetic field corresponding to a region inside the asteroid characteristic line is applied, the magnetization direction of free-magnetic layer VL does not change. Thus, data writing is not executed when a predetermined data write current flows only through one of write digit line WDL and write bit line WBL. The magnetization direction, i.e., storage data level, which is once written into the MTJ memory cell, will be nonvolatilely held until new data writing is executed.
FIG. 25 conceptually shows the data read operation for the MTJ memory cell.
Referring to FIG. 25, access transistor ATR is turned on in response to activation of word line WL in the data read operation. Thereby, magnetic tunnel junction MTJ is electrically coupled between write bit line WBL and read bit line RBL. Further, a sense current Is is supplied to a current path including magnetic tunnel junction MTJ and read bit line RBL so that a voltage change corresponding to the electric resistance of magnetic tunnel junction MTJ and thus corresponding to the storage data level of the MTJ memory cell can occur on read bit line RBL.
For example, therefore, supply of sense current Is may start after precharging read bit line RBL to a predetermined voltage. Thereby, the storage data of MTJ memory cell can be read by detecting a voltage on read bit line RBL.
In the data read operation, sense current Is flows through magnetic tunnel junction MTJ. However, the sense current Is is generally determined to be smaller by one or two digits than the data write current already described. This reduces a possibility that sense current Is affects to rewrite erroneously the storage data of the MTJ memory cell in the data read operation.
In an MRAM device having a plurality of MTJ memory cells arranged in rows and columns, write digit line WDL and word line WL are generally arranged corresponding to each memory cell row, and write bit line WBL and read bit line RBL are generally arranged corresponding to each memory cell column. Therefore, two kinds of interconnections, i.e., write digit line WDL used in the data write operation and word line WL used in the data read operation are required for each memory cell row. This disadvantageously increases an area of circuitry related to the row selecting operation.
As already described, it is also necessary to pass the data write current through both write bit line WBL and write digit line WDL for the selected memory cell, into which data is to be written. Therefore, the data write current is supplied through either of write bit line WBL or write digit line WDL for the unselected memory cells in the same memory cell row or the same memory cell column including the selected memory cell.
On the unselected memory cells, data writing is not effected in theory. However, there is a possibility that minute write operations are effected due to an influence by noises and others, and therefore causes change in the magnetization direction of the free-magnetic layer. When effects by such phenomena are accumulated, erroneous writing of data may occur, and the stored data may disappear. Accordingly, it has been demanded to provide a structure, which can suppress the possibility of such erroneous data writing into the data write operation.
Further, operation tests must be performed to evaluate sufficiently a resistance to the erroneous data writing into each MTJ memory cell. Therefore, it is also required to provide a structure, which can efficiently conduct such operation tests on the whole memory cell array.